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rev.2.10 aug 25, 2006 page 1 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) renesas mcu under development this document is under development and its contents are subject to change specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. rej03b0061-0210 rev.2.10 aug 25, 2006 1. overview the m16c/6n group (m16c/6nl, m16c/6nn) of mcus are built using the high-performance silicon gate cmos process using the m16c/60 series cpu core and are packaged in 100-pin and 128-pin plastic molded lqfp. these mcus operate using sophisticated instructions featuring a high level of instruction efficiency. with 1 mbyte of address space, they are capable of executing instructions at high speed. being equipped with one can (controller area network) module in the m16c/6n group (m16c/6nl, m16c/6nn), the mcu is suited to drive automotive and industrial control systems. the can module complies with the 2.0b specification. in addition, this mcu contains a multiplier and dmac which combined with fast instruction processing capability, makes it suitable for control of various oa, communication equipment which requires high-speed arithmetic/logic operations. 1.1 applications ?car audio and industrial control systems, other
rev.2.10 aug 25, 2006 page 2 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. 1.2 performance overview tables 1.1 and 1.2 list the functions and specifications for m16c/6n group (m16c/6nl, m16c/6nn). table 1.1 functions and specifications for m16c/6n group (100-pin version: m16c/6nl) item specification cpu number of fundamental 91 instructions instructions minimum instruction execution time 41.7ns (f(bclk) = 24 mhz, 1/1 prescaler, without software wait) operating mode single-chip, memory expansion and microprocessor modes address space 1 mbyte memory capacity refer to table 1.3 product information peripheral ports input/output: 87 pins, input: 1 pin function multifunction timers timer a: 16 bits ? 5 channels timer b: 16 bits ? 6 channels three-phase motor control circuit serial interfaces 3 channels clock synchronous, uart, i 2 c-bus (1) , iebus (2) 2 channels clock synchronous a/d converter 10-bit a/d converter: 1 circuit, 26 channels d/a converter 8 bits ? 2 channels dmac 2 channels crc calculation circuit crc-ccitt can module 1 channel with 2.0b specification watchdog timer 15 bits ? 1 channel (with prescaler) interrupts i nternal: 30 sources, e xternal: 9 sources software: 4 sources, priority levels: 7 levels clock generation circuits 4 circuits main clock oscillation circuit (*) sub clock oscillation circuit (*) on-chip oscillator pll frequency synthesizer (*) equipped with on-chip feedback resistor oscillation-stopped detector main clock oscillation stop and re-oscillation detection function electrical supply voltage vcc = 3.0 to 5.5 v characteristics (f(bclk) = 24 mhz, 1/1 prescaler, without software wait) consumption mask rom 19ma (f(bclk) = 24 mhz, pll operation, no division) current flash memory 21ma (f(bclk) = 24 mhz, pll operation, no division) mask rom 3a (f(bclk) = 32 khz, wait mode, oscillation capacity low) flash memory 0.8a (stop mode, topr = 25 c) flash memory programming and erasure voltage 3.3 0.3 v or 5.0 0.5 v version programming and erasure endurance 100 times i/o i/o withstand voltage 5.0 v characteristics output current 5m a operating ambient temperature -40 to 85 c device configuration cmos high-performance silicon gate package 100-pin molded-plastic lqfp notes: 1. i 2 c-bus is a trademark of koninklijke philips electronics n.v. 2. iebus is a trademark of nec electronics corporation.
rev.2.10 aug 25, 2006 page 3 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. table 1.2 functions and specifications for m16c/6n group (128-pin version: m16c/6nn) item specification cpu number of fundamental 91 instructions instructions minimum instruction execution time 41.7ns (f(bclk) = 24 mhz, 1/1 prescaler, without software wait) operating mode single-chip, memory expansion and microprocessor modes address space 1 mbyte memory capacity refer to table 1.3 product information peripheral ports input/output: 113 pins, input: 1 pin function multifunction timers timer a: 16 bits ? 5 channels timer b: 16 bits ? 6 channels three-phase motor control circuit serial interfaces 3 channels clock synchronous, uart, i 2 c-bus (1) , iebus (2) 4 channels clock synchronous a/d converter 10-bit a/d converter: 1 circuit, 26 channels d/a converter 8 bits ? 2 channels dmac 2 channels crc calculation circuit crc-ccitt can module 1 channel with 2.0b specification watchdog timer 15 bits ? 1 channel (with prescaler) interrupts internal: 32 sources, external: 12 sources software: 4 sources, priority levels: 7 levels clock generation circuits 4 circuits main clock oscillation circuit (*) sub clock oscillation circuit (*) on-chip oscillator pll frequency synthesizer (*) equipped with on-chip feedback resistor oscillation-stopped detector main clock oscillation stop and re-oscillation detection function electrical supply voltage vcc = 3.0 to 5.5 v characteristics (f(bclk) = 24 mhz, 1/1 prescaler, without software wait) consumption mask rom 19ma (f(bclk) = 24 mhz, pll operation, no division) current flash memory 21ma (f(bclk) = 24 mhz, pll operation, no division) mask rom 3a (f(bclk) = 32 khz, wait mode, oscillation capacity low) flash memory 0.8a (stop mode, topr = 25 c) flash memory programming and erasure voltage 3.3 0.3 v or 5.0 0.5 v version programming and erasure endurance 100 times i/o i/o withstand voltage 5.0 v characteristics output current 5m a operating ambient temperature -40 to 85 c device configuration cmos high-performance silicon gate package 128-pin molded-plastic lqfp notes: 1. i 2 c-bus is a trademark of koninklijke philips electronics n.v. 2. iebus is a trademark of nec electronics corporation.
rev.2.10 aug 25, 2006 page 4 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. 1.3 block diagram figure 1.1 shows a block diagram. figure 1.1 block diagram notes: 1: rom size depends on mcu type. 2: ram size depends on mcu type. 3: ports p11 to p14 are only in the 128-pin version. 4: 8 bits ? 2 channels in the 100-pin version. port p11 8 (3) 2 port p14 (3) 8 port p12 (3) 8 port p13 (3) timer (16 bits) output (timer a): 5 input (timer b): 6 three-phase motor control circuit internal peripheral functions watchdog timer (15 bits) a/d converter (10 bits ? 8 channels expandable up to 26 channels) uart or clock synchronous serial i/o (3 channels) system clock generation circuit xin-xout xcin-xcout pll frequency synthesizer on-chip oscillator port p0 8 port p1 8 port p2 8 8 8 8 port p6 8 8 7 8 8 port p10 port p9 port p8_5 port p8 port p7 port p5 port p4 port p3 clock synchronous serial i/o (8 bits ? 4 channels) (4) can module (1 channel) dmac (2 channels) d/a converter (8 bits ? 2 channels) memory m16c/60 series cpu core r0h r0l r1h r1l r2 r3 a0 a1 fb multiplier intb pc usp isp sb flg rom (1) ram (2) crc calculation circuit (ccitt) (polynomial: x 16 +x 12 +x 5 +1)
rev.2.10 aug 25, 2006 page 5 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. 1.4 product information table 1.3 lists the product information and figure 1.2 shows the type number, mem ory size, and packages. table 1.3 product information as of aug. 2006 figure 1.2 type number, memory size, and package type no. m30 6n l m g - xxx gp package type: gp: package plqp0100kb-a (100p6q-a) plqp0128kb-a (128p6q-a) rom no. omitted on flash memory version rom capacity: e : 192 kbytes g: 256 kbytes h : 384 kbytes j : 512 kbytes memory type: m : mask rom version f : flash memory version shows the number of can module, pin count, etc. 6n group m16c family notes: 1. data flash memory provides an additional 4 kbytes of rom capacity (block a). 2. the correspondence between new and old package types is as follows. plqp0100kb-a: 100p6q-a plqp0128kb-a: 128p6q-a type no. rom capacity ram capacity package type (2) remarks m306nlfhgp 384 k + 4 kbytes 31 kbytes plqp0100kb-a flash memory m306nnfhgp plqp0128kb-a version (1) m306nlfjgp 512 k + 4 kbytes 31 kbytes plqp0100kb-a m306nnfjgp plqp0128kb-a m306nlme-xxxgp 192 kbytes 16 kbytes plqp0100kb-a mask rom version m306nnme-xxxgp plqp0128kb-a m306nlmg-xxxgp 256 kbytes 20 kbytes plqp0100kb-a m306nnmg-xxxgp plqp0128kb-a
rev.2.10 aug 25, 2006 page 6 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. 1.5 pin assignments figures 1.3 and 1.4 show the pin assignment (top view). tables 1.4 to1.8 list the list of pin names. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 p7_4/ta2out/w(clk4) p7_6/ta3out p5_6/ale p7_7/ta3in p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd vcc2 vss p5_7/rdy/clkout p4_5/cs1 p4_6/cs2 p4_7/cs3 avcc p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/crx0/clk4 p9_6/anex1/ctx0/sout4 (1) p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_0/ta4out/u(sin4) p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p8_2/int0 p8_3/int1 p8_5/nmi p9_7/adtrg/sin4 p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p8_4/int2/zp p7_2/clk2/ta1out/v p7_1/rxd2/scl2/ta0in/tb5in (1) p7_0/txd2/sda2/ta0out p7_5/ta2in/w(sout4) p7_3/cts2/rts2/ta1in/v p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p8_1/ta4in/u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 m16c/6n group (m16c/6nl) figure 1.3 pin assignments (top view) (1) package: plqp0100kb-a (100p6q-a) note: 1. p7_1 and p9_1 are n channel open-drain pins.
rev.2.10 aug 25, 2006 page 7 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. table 1.4 list of pin names for 100-pin package (1) pin no. control port interrupt timer pin uart pin analog can module bus control pin pin pin pin pin 1 p9_4 tb4in da1 2 p9_3 tb3in da0 3 p9_2 tb2in sout3 4 p9_1 tb1in sin3 5 p9_0 tb0in clk3 6 byte 7 cnvss 8 xcin p8_7 9 xcout p8_6 10 _____________ reset 11 xout 12 vss 13 xin 14 vcc1 15 p8_5 ________ nmi 16 p8_4 _________ int2 zp 17 p8_3 _________ int1 18 p8_2 _________ int0 19 p8_1 ___ ta4in/u 20 p8_0 ta4out/u (sin4) 21 p7_7 ta3in 22 p7_6 ta3out 23 p7_5 ____ ta2in/w (sout4) 24 p7_4 ta2out/w (clk4) 25 p7_3 ___ ta1in/v __________ __________ cts2/rts2 26 p7_2 ta1out/v clk2 27 p7_1 ta0in/tb5in rxd2/scl2 28 p7_0 ta0out txd2/sda2 29 p6_7 txd1/sda1 30 p6_6 rxd1/scl1 31 p6_5 clk1 32 p6_4 _________ _________ _________ cts1/rts1/cts0/clks1 33 p6_3 txd0/sda0 34 p6_2 rxd0/scl0 35 p6_1 clk0 36 p6_0 __________ __________ cts0/rts0 37 p5_7 _________ rdy/clkout 38 p5_6 ale 39 p5_5 ___________ hold 40 p5_4 ___________ hlda 41 p5_3 bclk 42 p5_2 ______ rd 43 p5_1 __________________ wrh/bhe 44 p5_0 _________ ______ wrl/wr 45 p4_7 _______ cs3 46 p4_6 _______ cs2 47 p4_5 _______ cs1 48 p4_4 _______ cs0 49 p4_3 a19 50 p4_2 a18
rev.2.10 aug 25, 2006 page 8 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. pin no. control port interrupt timer pin uart pin analog can module bus control pin pin pin pin pin 51 p4_1 a17 52 p4_0 a16 53 p3_7 a15 54 p3_6 a14 55 p3_5 a13 56 p3_4 a12 57 p3_3 a11 58 p3_2 a10 59 p3_1 a9 60 vcc2 61 p3_0 a8(/-/d7) 62 vss 63 p2_7 an2_7 a7(/d7/d6) 64 p2_6 an2_6 a6(/d6/d5) 65 p2_5 an2_5 a5(/d5/d4) 66 p2_4 an2_4 a4(/d4/d3) 67 p2_3 an2_3 a3(/d3/d2) 68 p2_2 an2_2 a2(/d2/d1) 69 p2_1 an2_1 a1(/d1/d0) 70 p2_0 an2_0 a0(/d0/-) 71 p1_7 _________ int5 d15 72 p1_6 _________ int4 d14 73 p1_5 _________ int3 d13 74 p1_4 d12 75 p1_3 d11 76 p1_2 d10 77 p1_1 d9 78 p1_0 d8 79 p0_7 an0_7 d7 80 p0_6 an0_6 d6 81 p0_5 an0_5 d5 82 p0_4 an0_4 d4 83 p0_3 an0_3 d3 84 p0_2 an0_2 d2 85 p0_1 an0_1 d1 86 p0_0 an0_0 d0 87 p10_7 ______ ki3 an7 88 p10_6 ______ ki2 an6 89 p10_5 ______ ki1 an5 90 p10_4 ______ ki0 an4 91 p10_3 an3 92 p10_2 an2 93 p10_1 an1 94 avss 95 p10_0 an0 96 vref 97 avcc 98 p9_7 sin4 ______________ adtrg 99 p9_6 sout4 anex1 ctx0 100 p9_5 clk4 anex0 crx0 table 1.5 list of pin names for 100-pin package (2)
rev.2.10 aug 25, 2006 page 9 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. figure 1.4 pin assignments (top view) (2) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 104 105 106 107 108 64 103 p5_7/rdy/clkout p9_5/anex0/crx0/clk4 p9_6/anex1/ctx0/sout4 p14_1 p14_0 p13_7/int8 p13_6/int7 p13_5/int6 p13_4 p1_3/d11 p1_4/d12 p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p11_3 p11_2/sout5 p11_1/sin5 p11_0/clk5 vcc1 vss p13_0 p13_1 p13_2 p13_3 p12_5 p12_6 p12_7 p11_4 p11_5/clk6 p11_6/sout6 p11_7/sin6 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 29 30 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 72 71 70 69 68 67 66 65 82 81 80 79 78 77 76 75 74 73 92 91 90 89 88 87 86 85 84 83 102 101 100 99 98 97 96 95 94 93 p1_1/d9 p1_2/d10 p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 p4_4/cs0 p12_0 p12_1 p12_2 p12_3 p12_4 p4_5/cs1 p4_6/cs2 p4_7/cs3 vcc2 vss p5_6/ale p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p5_0/wrl/wr p5_1/wrh/bhe p7_2/clk2/ta1out/v (1) p7_1/rxd2/scl2/ta0in/tb5in p7_0/txd2/sda2/ta0out vcc1 p7_4/ta2out/w(clk4) p7_6/ta3out p7_7/ta3in p8_0/ta4out/u(sin4) p8_2/int0 p8_3/int1 p8_5/nmi p8_4/int2/zp p7_5/ta2in/w(sout4) p7_3/cts2/rts2/ta1in/v p8_1/ta4in/u xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p9_3/da0/tb3in p9_4/da1/tb4in (1) p9_1/tb1in/sin3 p9_2/tb2in/sout3 p9_0/tb0in/clk3 p9_7/adtrg/sin4 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 vref avss avcc p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 m16c/6n group (m16c/6nn) note: 1. p7_1 and p9_1 are n channel open-drain pins. package: plqp0128kb-a (128p6q-a)
rev.2.10 aug 25, 2006 page 10 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. table 1.6 list of pin names for 128-pin package (1) pin no. control port interrupt timer pin uart pin analog can module bus control pin pin pin pin pin 1 vref 2 avcc 3 p9_7 sin4 ______________ adtrg 4 p9_6 sout4 anex1 ctx0 5 p9_5 clk4 anex0 crx0 6 p9_4 tb4in da1 7 p9_3 tb3in da0 8 p9_2 tb2in sout3 9 p9_1 tb1in sin3 10 p9_0 tb0in clk3 11 p14_1 12 p14_0 13 byte 14 cnvss 15 xcin p8_7 16 xcout p8_6 17 _____________ reset 18 xout 19 vss 20 xin 21 vcc1 22 p8_5 ________ nmi 23 p8_4 _________ int2 zp 24 p8_3 _________ int1 25 p8_2 _________ int0 26 p8_1 ___ ta4in/u 27 p8_0 ta4out/u (sin4) 28 p7_7 ta3in 29 p7_6 ta3out 30 p7_5 ____ ta2in/w (sout4) 31 p7_4 ta2out/w (clk4) 32 p7_3 ___ ta1in/v __________ __________ cts2/rts2 33 p7_2 ta1out/v clk2 34 p7_1 ta0in/tb5in rxd2/scl2 35 p7_0 ta0out txd2/sda2 36 p6_7 txd1/sda1 37 vcc1 38 p6_6 rxd1/scl1 39 vss 40 p6_5 clk1 41 p6_4 _________ _________ _________ cts1/rts1/cts0/clks1 42 p6_3 txd0/sda0 43 p6_2 rxd0/scl0 44 p6_1 clk0 45 p6_0 __________ __________ cts0/rts0 46 p13_7 _________ int8 47 p13_6 _________ int7 48 p13_5 _________ int6 49 p13_4 50 p5_7 _________ rdy/clkout
rev.2.10 aug 25, 2006 page 11 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. pin no. control port interrupt timer pin uart pin analog can module bus control pin pin pin pin pin 51 p5_6 ale 52 p5_5 ___________ hold 53 p5_4 ___________ hlda 54 p13_3 55 p13_2 56 p13_1 57 p13_0 58 p5_3 bclk 59 p5_2 ______ rd 60 p5_1 __________________ wrh/bhe 61 p5_0 _________ ______ wrl/wr 62 p12_7 63 p12_6 64 p12_5 65 p4_7 _______ cs3 66 p4_6 _______ cs2 67 p4_5 _______ cs1 68 p4_4 _______ cs0 69 p4_3 a19 70 p4_2 a18 71 p4_1 a17 72 p4_0 a16 73 p3_7 a15 74 p3_6 a14 75 p3_5 a13 76 p3_4 a12 77 p3_3 a11 78 p3_2 a10 79 p3_1 a9 80 p12_4 81 p12_3 82 p12_2 83 p12_1 84 p12_0 85 vcc2 86 p3_0 a8(/-/d7) 87 vss 88 p2_7 an2_7 a7(/d7/d6) 89 p2_6 an2_6 a6(/d6/d5) 90 p2_5 an2_5 a5(/d5/d4) 91 p2_4 an2_4 a4(/d4/d3) 92 p2_3 an2_3 a3(/d3/d2) 93 p2_2 an2_2 a2(/d2/d1) 94 p2_1 an2_1 a1(/d1/d0) 95 p2_0 an2_0 a0(/d0/-) 96 p1_7 _________ int5 d15 97 p1_6 _________ int4 d14 98 p1_5 _________ int3 d13 99 p1_4 d12 100 p1_3 d11 table 1.7 list of pin names for 128-pin package (2)
rev.2.10 aug 25, 2006 page 12 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. pin no. control port interrupt timer pin uart pin analog can module bus control pin pin pin pin pin 101 p1_2 d10 102 p1_1 d9 103 p1_0 d8 104 p0_7 an0_7 d7 105 p0_6 an0_6 d6 106 p0_5 an0_5 d5 107 p0_4 an0_4 d4 108 p0_3 an0_3 d3 109 p0_2 an0_2 d2 110 p0_1 an0_1 d1 111 p0_0 an0_0 d0 112 p11_7 sin6 113 p11_6 sout6 114 p11_5 clk6 115 p11_4 116 p11_3 117 p11_2 sout5 118 p11_1 sin5 119 p11_0 clk5 120 p10_7 ______ ki3 an7 121 p10_6 ______ ki2 an6 122 p10_5 ______ ki1 an5 123 p10_4 ______ ki0 an4 124 p10_3 an3 125 p10_2 an2 126 p10_1 an1 127 avss 128 p10_0 an0 table 1.8 list of pin names for 128-pin package (3)
rev.2.10 aug 25, 2006 page 13 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. 1.6 pin functions tables 1.9 to 1.11 list the pin functions. table 1.9 pin functions (100-pin and 128-pin versions) (1) i i i i i i/o i/o o i/o i/o o o o i o i vcc1, vcc2, vss avcc, avss _____________ reset cnvss byte d0 to d7 d8 to d15 a0 to a19 a0/d0 to a7/d7 a1/d0 to a8/d7 _______ _______ cs0 to cs3 _________ ______ wrl/wr _________ ________ wrh/bhe ______ rd ale __________ hold __________ hlda ________ rdy power supply input analog power supply input reset input cnvss external data bus width select input bus control pins apply 3.0 to 5.5 v to the vcc1 and vcc2 pins and 0 v to the vss pin. the vcc apply condition is that vcc2 = vcc1 (1) . applies the power supply for the a/d converter. connect the avcc pin to vcc1. connect the avss pin to vss. the mcu is in a reset state when applying l to the this pin. switches processor mode. connect this pin to vss to when after a reset to start up in single-chip mode. connect this pin to vcc1 to start up in microprocessor mode. switches the data bus in external memory space. the data bus is 16-bit long when the this pin is held l and 8-bit long when the this pin is held h . set it to either one. connect this pin to vss when single-chip mode. inputs and outputs data (d0 to d7) when these pins are set as the separate bus. inputs and outputs data (d8 to d15) when external 16-bit data bus is set as the separate bus. output address bits (a0 to a19). input and output data (d0 to d7) and output address bits (a0 to a7) by time-sharing when external 8-bit data bus are set as the multiplexed bus. input and output data (d0 to d7) and output address bits (a1 to a8) by time-sharing when external 16-bit data bus are set as the multiplexed bus. _______ _______ _______ _______ output cs0 to cs3 signals. cs0 to cs3 are chip-select signals to specify an external space. ________ _________ ______ ________ _____ ________ _________ output wrl, wrh, (wr, bhe), rd signals. wrl and wrh or ________ ______ bhe, and wr can be switched by program. ________ _________ _____ wrl, wrh, and rd are selected ________ the wrl signal becomes l by writing data to an even address in an external memory space. _________ the wrh signal becomes l by writing data to an odd address in an external memory space. _____ the rd pin signal becomes l by reading data in an external memory space. ______ ________ _____ wr, bhe, and rd are selected ______ the wr signal becomes l by writing data in an external memory space. _____ the rd signal becomes l by reading data in an external memory space. ________ the bhe signal becomes l by accessing an odd address. ______ ________ _____ select wr, bhe, and rd for an external 8-bit data bus. ale is a signal to latch the address. __________ while the hold pin is held l , the mcu is placed in a hold state. __________ in a hold state, hlda outputs a l signal. ________ while applying a l signal to the rdy pin, the mcu is placed in a wait state. signal name pin name i/o type description i: input o: output i/o: input/output note: 1. in this manual, hereafter, vcc refers to vcc1 unless otherwise noted.
rev.2.10 aug 25, 2006 page 14 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. table 1.10 pin functions (100-pin and 128-pin versions) (2) i o i o o o i i i i/o i i i o i o i/o i i o o o i/o i/o i i i i/o i o i o xin xout xcin xcout bclk clkout nt0 to int8 (2) ________ nmi ______ ______ ki0 to ki3 ta0out to ta4out ta0in to ta4in zp tb0in to tb5in ___ ___ ____ u, u, v, v, w, w __________ __________ cts0 to cts2 __________ __________ rts0 to rts2 clk0 to clk6 (2) rxd0 to rxd2 sin3 to sin6 (2) txd0 to txd2 sout3 to sout6 (2) clks1 sda0 to sda2 scl0 to scl2 vref an0 to an7 an0_0 to an0_7 an2_0 to an2_7 _____________ adtrg anex0 anex1 da0, da1 crx0 ctx0 main clock input main clock output sub clock input sub clock output bclk output clock output int interrupt input _______ nmi interrupt input key input interrupt input timer a timer b three-phase motor control output serial interface i 2 c mode reference voltage input a/d converter d/a converter can module i/o pins for the main clock oscillation circuit. connect a ceramic resonator or crystal oscillator between xin and xout (1) . to use the external clock, input the clock from xin and leave xout open. i/o pins for a sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout (1) . to use the external clock, input the clock from xcin and leave xcout open. outputs the bclk signal. the clock of the same cycle as fc, f8, or f32 is output. ______ input pins for the int interrupt. _______ input pin for the nmi interrupt. input pins for the key input interrupt. these are timer a0 to timer a4 i/o pins. these are timer a0 to timer a4 input pins. input pin for the z-phase. these are timer b0 to timer b5 input pins. these are three-phase motor control output pins. these are transmit control input pins. these are receive control output pins. these are transfer clock i/o pins. these are serial data input pins. these are serial data input pins. these are serial data output pins. these are serial data output pins. this is output pin for transfer clock output from multiple pins function. these are serial data i/o pins. these are transfer clock i/o pins. ( however, scl2 for the n-channel open drain output.) applies the reference voltage for the a/d converter and d/a converter. analog input pins for the a/d converter. this is an a/d trigger input pin. this is the extended analog input pin for the a/d converter, and is the output in external op-amp connection mode. this is the extended analog input pin for the a/d converter. these are the output pins for the d/a converter. this is the input pin for the can module. this is the output pin for the can module. signal name pin name i/o type description i: input o: output i/o: input/output notes: 1. ask the oscillator maker the oscillation characteristic. ________ ________ 2. int6 to int8, clk5, clk6, sin5, sin6, sout5, sout6 are only in the 128-pin version.
rev.2.10 aug 25, 2006 page 15 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 1. overview under development this document is under development and its contents are subject to change. table 1.11 pin functions (100-pin and 128-pin versions) (3) 8-bit i/o ports in cmos, having a direction register to select an input or output. each pin is set as an input port or output port. an input port can be set for a pull-up or for no pull-up in 4-bit unit by program. (however p7_1 and p9_1 for the n-channel open drain output.) _______ input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. i/o port input port p0_0 to p0_7 p1_0 to p1_7 p2_0 to p2_7 p3_0 to p3_7 p4_0 to p4_7 p5_0 to p5_7 p6_0 to p6_7 p7_0 to p7_7 p8_0 to p8_4 p8_6, p8_7 p9_0 to p9_7 p10_0 to p10_7 p11_0 to p11_7 (1) p12_0 to p12_7 (1) p13_0 to p13_7 (1) p14_0, p14_1 (1) p8_5 i/o i signal name pin name i/o type description i: input o: output i/o: input/output note: 1. ports p11 to p14 are only in the 128-pin version.
rev.2.10 aug 25, 2006 page 16 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 2. central processing unit (cpu) under development this document is under development and its contents are subject to change. figure 2.1 cpu registers 2.1 data registers (r0, r1, r2, and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) the a0 register consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and arithmetic/logic operations. a1 is the same as a0. in some instructions, a1 and a0 can be combined for use as a 32-bit address register (a1a0). 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two register banks. sb usp isp b15 b0 static base register user stack pointer interrupt stack pointer b19 b15 intbl intbh the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl. b0 interrupt table register b19 pc b0 program counter r0h (r0's high bits) r0l (r0's low bits) r1h (r1's high bits) r1l (r1's low bits) r2 r3 b31 b15 b8 b7 b0 r2 r3 a0 a1 fb data registers (1) address registers (1) frame base registers (1) note: 1. these registers comprise a register bank. there are two register banks. b15 b0 carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area b15 b0 flg flag register ipl u i o b s z d c b7 b8
rev.2.10 aug 25, 2006 page 17 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 2. central processing unit (cpu) under development this document is under development and its contents are subject to change. 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp), interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) this flag is used exclusively for debugging purpose. during normal use, set to 0. 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0. 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0; register bank 1 is selected when this flag is 1. 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0, and are enabled when the i flag is 1. the i flag is set to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0; usp is selected when the u flag is 1. the u flag is set to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt request is enabled. 2.8.10 reserved area when white to this bit, write 0. when read, its content is undefined.
rev.2.10 aug 25, 2006 page 18 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 3. memory under development this document is under development and its contents are subject to change. 3. memory figure 3.1 shows a memory map. the address space extends the 1 mbyte from address 00000h to fffffh. the internal rom is allocated in a lower address direction beginning with address fffffh. for example, a 512-kbyte internal rom is allocated to the addresses from 80000h to fffffh. as for the flash memory version, 4-kbyte space (block a) exists in 0f000h to 0ffffh. 4-kbyte space is mainly for storing data. in addition to storing data, 4-kbyte space also can store programs. the fixed interrupt vector table is allocated to the addresses from fffdch to fffffh. therefore, store the start address of each interrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400h. for example, a 31-kbyte internal ram is allocated to the addresses from 00400h to 07fffh. in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are generated. the special function registers (sfrs) are allocated to the addresses from 00000h to 003ffh. peripheral function control registers are located here. of the sfr, any area which has no functions allocated is reserved for future use and cannot be accessed by user. the special page vector table is allocated to the addresses from ffe00h to fffdbh. this vector is used by the jmps or jsrs instruction. for details, refer to m16c/60, m16c/20, m16c/tiny series software manual . in memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. figure 3.1 memory map 00000h yyyyy h fffffh 00400h 0ffffh 10000h 0f000h 27000h 28000h 80000h xxxxx h internal rom (data flash) (3) internal rom (program area) (4) sfr internal ram reserved area external area reserved area (2) external area ffe00h fffdch fffffh notes: 1. during memory expansion mode or microprocessor mode, cannot be used. 2. in memory expansion mode, cannot be used. 3. as for the flash memory version, 4-kbyte space (block a) exists. 4. when using the masked rom version, write nothing to internal rom area. 5. shown here is a memory map for the case where the pm10 bit in the pm1 register is 1 (block a enabled, addresses 10000h to 26fffh for cs2 area) and the pm13 bit in the pm1 register is 1 (internal ram area is expanded over 192 kbytes). undefined instruction overflow brk instruction address match single step oscillation stop and re-oscillation detection / watchdog timer reset special page vector table dbc nmi reserved area (1) address xxxxx h capacity internal ram 20 kbytes 31 kbytes 053ff h 16 kbytes 043ff h 07fff h address yyyyy h capacity internal rom (4) 384 kbytes a0000 h 256 kbytes c0000 h 192 kbytes d0000 h 512 kbytes 80000 h
rev.2.10 aug 25, 2006 page 19 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.12 list the sfr information. table 4.1 sfr information (1) (3) 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000ah 000bh 000ch 000dh 000eh 000fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh processor mode register 0 (1) processor mode register 1 system clock control register 0 system clock control register 1 chip select control register address match interrupt enable register protect register oscillation stop detection register (2) watchdog timer start register watchdog timer control register address match interrupt register 0 address match interrupt register 1 chip select expansion control register pll control register 0 processor mode register 2 dma0 source pointer dma0 destination pointer dma0 transfer counter dma0 control register dma1 source pointer dma1 destination pointer dma1 transfer counter dma1 control register pm0 pm1 cm0 cm1 csr aier prcr cm2 wdts wdc rmad0 rmad1 cse plc0 pm2 sar0 dar0 tcr0 dm0con sar1 dar1 tcr1 dm1con x: undefined notes: 1. bits pm00 and pm01 in the pm0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset. 2. bits cm20, cm21, and cm27 in the cm2 register do not change at oscillation stop detection reset. 3. blank spaces are reserved. no access is allowed. address register symbol after reset 00000000b (cnvss pin is "l") 00000011b (cnvss pin is "h") 00001000b 01001000b 00100000b 00000001b xxxxxx00b xx000000b 0x000000b xxh 00xxxxxxb 00h 00h x0h 00h 00h x0h 00h 0001x010b xxx00000b xxh xxh xxh xxh xxh xxh xxh xxh 00000x00b xxh xxh xxh xxh xxh xxh xxh xxh 00000x00b
rev.2.10 aug 25, 2006 page 20 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. table 4.2 sfr information (2) (2) can0 wake-up interrupt control register can0 successful reception interrupt control register can0 successful transmission interrupt control register int3 interrupt control register timer b5 interrupt control register si/o5 interrupt control register (1) timer b4 interrupt control register uart1 bus collision detection interrupt control register timer b3 interrupt control register uart0 bus collision detection interrupt control register si/o4 interrupt control register int5 interrupt control register si/o3 interrupt control register int4 interrupt control register uart2 bus collision detection interrupt control register dma0 interrupt control register dma1 interrupt control register can0 error interrupt control register a/d conversion interrupt control register key input interrupt control register uart2 transmit interrupt control register uart2 receive interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register int7 interrupt control register (1) timer a3 interrupt control register int6 interrupt control register (1) timer a4 interrupt control register timer b0 interrupt control register si/o6 interrupt control register (1) timer b1 interrupt control register int8 interrupt control register (1) timer b2 interrupt control register int0 interrupt control register int1 interrupt control register int2 interrupt control register can0 message box 0: identifier / dlc can0 message box 0: data field can0 message box 0: time stamp can0 message box 1: identifier / dlc can0 message box 1: data field can0 message box 1: time stamp 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh address register xxxxx000b xxxxx000b xxxxx000b xx00x000b xxxxx000b xxxxx000b xxxxx000b xx00x000b xx00x000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xx00x000b xx00x000b xxxxx000b xxxxx000b xx00x000b xxxxx000b xx00x000b xx00x000b xx00x000b xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh c01wkic c0recic c0trmic int3ic tb5ic s5ic tb4ic u1bcnic tb3ic u0bcnic s4ic int5ic s3ic int4ic u2bcnic dm0ic dm1ic c01erric adic kupic s2tic s2ric s0tic s0ric s1tic s1ric ta0ic ta1ic ta2ic int7ic ta3ic int6ic ta4ic tb0ic s6ic tb1ic int8ic tb2ic int0ic int1ic int2ic symbol after reset x: undefined notes: 1. these registers exist only in the 128-pin version. 2. blank spaces are reserved. no access is allowed.
rev.2.10 aug 25, 2006 page 21 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. table 4.3 sfr information (3) x: undefined 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h 00a1h 00a2h 00a3h 00a4h 00a5h 00a6h 00a7h 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh 00bch 00bdh 00beh 00bfh can0 message box 2: identifier / dlc can0 message box 2: data field can0 message box 2: time stamp can0 message box 3: identifier / dlc can0 message box 3: data field can0 message box 3: time stamp can0 message box 4: identifier / dlc can0 message box 4: data field can0 message box 4: time stamp can0 message box 5: identifier / dlc can0 message box 5: data field can0 message box 5: time stamp address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh
rev.2.10 aug 25, 2006 page 22 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. table 4.4 sfr information (4) x: undefined 00c0h 00c1h 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h 00d5h 00d6h 00d7h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h 00e1h 00e2h 00e3h 00e4h 00e5h 00e6h 00e7h 00e8h 00e9h 00eah 00ebh 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh can0 message box 6: identifier / dlc can0 message box 6: data field can0 message box 6: time stamp can0 message box 7: identifier / dlc can0 message box 7: data field can0 message box 7: time stamp can0 message box 8: identifier / dlc can0 message box 8: data field can0 message box 8: time stamp can0 message box 9: identifier / dlc can0 message box 9: data field can0 message box 9: time stamp address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh
rev.2.10 aug 25, 2006 page 23 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. table 4.5 sfr information (5) x: undefined 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010ah 010bh 010ch 010dh 010eh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011ah 011bh 011ch 011dh 011eh 011fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012ah 012bh 012ch 012dh 012eh 012fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh can0 message box 10: identifier / dlc can0 message box 10: data field can0 message box 10: time stamp can0 message box 11: identifier / dlc can0 message box 11: data field can0 message box 11: time stamp can0 message box 12: identifier / dlc can0 message box 12: data field can0 message box 12: time stamp can0 message box 13: identifier / dlc can0 message box 13: data field can0 message box 13: time stamp address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh
rev.2.10 aug 25, 2006 page 24 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. table 4.6 sfr information (6) (1) x: undefined note: 1. blank spaces are reserved. no access is allowed. 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh can0 message box 14: identifier /dlc can0 message box 14: data field can0 message box 14: time stamp can0 message box 15: identifier /dlc can0 message box 15: data field can0 message box 15: time stamp can0 global mask register can0 local mask a register can0 local mask b register address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh c0gmr c0lmar c0lmbr
rev.2.10 aug 25, 2006 page 25 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. table 4.7 sfr information (7) (2) x: undefined notes: 1. these registers are included in the flash memory version. cannot be accessed by users in the mask rom version. 2. blank spaces are reserved. no access is allowed. 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h 01b3h 01b4h 01b5h 01b6h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh flash memory control register 1 (1) flash memory control register 0 (1) address match interrupt register 2 address match interrupt enable register 2 address match interrupt register 3 fmr1 fmr0 rmad2 aier2 rmad3 address register symbol after reset 0x00xx0xb 00000001b 00h 00h x0h xxxxxx00b 00h 00h x0h
rev.2.10 aug 25, 2006 page 26 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. table 4.8 sfr information (8) (3) timer b3, b4, b5 count start flag timer a1-1 register timer a2-1 register timer a4-1 register three-phase pwm control register 0 three-phase pwm control register 1 three-phase output buffer register 0 three-phase output buffer register 1 dead time timer timer b2 interrupt generation frequency set counter interrupt source select register 2 timer b3 register timer b4 register timer b5 register si/o6 transmit/receive register (1) si/o6 control register (1) si/o6 bit rate register (1) si/o3, 4, 5, 6 transmit/receive register (2) timer b3 mode register timer b4 mode register timer b5 mode register interrupt source select register 0 interrupt source select register 1 si/o3 transmit/receive register si/o3 control register si/o3 bit rate register si/o4 transmit/receive register si/o4 control register si/o4 bit rate register si/o5 transmit/receive register (1) si/o5 control register (1) si/o5 bit rate register (1) uart0 special mode register 4 uart0 special mode register 3 uart0 special mode register 2 uart0 special mode register uart1 special mode register 4 uart1 special mode register 3 uart1 special mode register 2 uart1 special mode register uart2 special mode register 4 uart2 special mode register 3 uart2 special mode register 2 uart2 special mode register uart2 transmit/receive mode register uart2 bit rate register uart2 transmit buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register 01c0h 01c1h 01c2h 01c3h 01c4h 01c5h 01c6h 01c7h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h 01e1h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h 01f1h 01f2h 01f3h 01f4h 01f5h 01f6h 01f7h 01f8h 01f9h 01fah 01fbh 01fch 01fdh 01feh 01ffh address register symbol after reset tbsr ta11 ta21 ta41 invc0 invc1 idb0 idb1 dtt ictb2 ifsr2 tb3 tb4 tb5 s6trr s6c s6brg s3456trr tb3mr tb4mr tb5mr ifsr0 ifsr1 s3trr s3c s3brg s4trr s4c s4brg s5trr s5c s5brg u0smr4 u0smr3 u0smr2 u0smr u1smr4 u1smr3 u1smr2 u1smr u2smr4 u2smr3 u2smr2 u2smr u2mr u2brg u2tb u2c0 u2c1 u2rb 000xxxxxb xxh xxh xxh xxh xxh xxh 00h 00h 00111111b 00111111b xxh xxh x0000000b xxh xxh xxh xxh xxh xxh xxh 01000000b xxh xxxx0000b 00xx0000b 00xx0000b 00xx0000b 00h 00h xxh 01000000b xxh xxh 01000000b xxh xxh 01000000b xxh 00h 000x0x0xb x0000000b x0000000b 00h 000x0x0xb x0000000b x0000000b 00h 000x0x0xb x0000000b x0000000b 00h xxh xxh xxh 00001000b 00000010b xxh xxh x: undefined notes: 1. these registers exist only in the 128-pin version. 2. bits s5trf and s6trf in the s3456trr register are used in the 128-pin version. 3. blank spaces are reserved. no access is allowed.
rev.2.10 aug 25, 2006 page 27 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. x: undefined note: 1. blank spaces are reserved. no access is allowed. 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020ah 020bh 020ch 020dh 020eh 020fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021ah 021bh 021ch 021dh 021eh 021fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022ah 022bh 022ch 022dh 022eh 022fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023ah 023bh 023ch 023dh 023eh 023fh can0 message control register 0 can0 message control register 1 can0 message control register 2 can0 message control register 3 can0 message control register 4 can0 message control register 5 can0 message control register 6 can0 message control register 7 can0 message control register 8 can0 message control register 9 can0 message control register 10 can0 message control register 11 can0 message control register 12 can0 message control register 13 can0 message control register 14 can0 message control register 15 can0 control register can0 status register can0 slot status register can0 interrupt control register can0 extended id register can0 configuration register can0 receive error count register can0 transmit error count register can0 time stamp register can1 control register c0mctl0 c0mctl1 c0mctl2 c0mctl3 c0mctl4 c0mctl5 c0mctl6 c0mctl7 c0mctl8 c0mctl9 c0mctl10 c0mctl11 c0mctl12 c0mctl13 c0mctl14 c0mctl15 c0ctlr c0str c0sstr c0icr c0idr c0conr c0recr c0tecr c0tsr c1ctlr address register symbol after reset 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h x0000001b xx0x0000b 00h x0000001b 00h 00h 00h 00h 00h 00h xxh xxh 00h 00h 00h 00h x0000001b xx0x0000b table 4.9 sfr information (9) (1)
rev.2.10 aug 25, 2006 page 28 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. x: undefined note: 1. blank spaces are reserved. no access is allowed. xxh xxh 00h 00h can0 acceptance filter support register peripheral clock select register can0 clock select register 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024ah 024bh 024ch 024dh 024eh 024fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh 025fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026ah 026bh 026ch 026dh 026eh 026fh 0270h to 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037ah 037bh 037ch 037dh 037eh 037fh c0afs pclkr cclkr address register symbol after reset table 4.10 sfr information (10) (1)
rev.2.10 aug 25, 2006 page 29 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. x: undefined notes: 1. bits ta2p to ta4p in the udf register are set to 0 after reset. however, the contents in these bits are undefined when read. 2. blank spaces are reserved. no access is allowed. 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038ah 038bh 038ch 038dh 038eh 038fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039ah 039bh 039ch 039dh 039eh 039fh 03a0h 03a1h 03a2h 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh 03b0h 03b1h 03b2h 03b3h 03b4h 03b5h 03b6h 03b7h 03b8h 03b9h 03bah 03bbh 03bch 03bdh 03beh 03bfh count start flag clock prescaler reset flag one-shot start flag trigger select register up/down flag timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register timer b2 special mode register uart0 transmit/receive mode register uart0 bit rate register uart0 transmit buffer register uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 bit rate register uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register uart transmit/receive control register 2 dma0 request source select register dma1 request source select register crc data register crc input register tabsr cpsrf onsf trgsr udf ta0 ta1 ta2 ta3 ta4 tb0 tb1 tb2 ta0mr ta1mr ta2mr ta3mr ta4mr tb0mr tb1mr tb2mr tb2sc u0mr u0brg u0tb u0c0 u0c1 u0rb u1mr u1brg u1tb u1c0 u1c1 u1rb ucon dm0sl dm1sl crcd crcin address register symbol after reset 00h 0xxxxxxxb 00h 00h 00h xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh 00h 00h 00h 00h 00h 00xx0000b 00xx0000b 00xx0000b xxxxxx00b 00h xxh xxh xxh 00001000b 00xx0010b xxh xxh 00h xxh xxh xxh 00001000b 00xx0010b xxh xxh x0000000b 00h 00h xxh xxh xxh (1) table 4.11 sfr information (11) (2)
rev.2.10 aug 25, 2006 page 30 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 4. special function registers (sfrs) under development this document is under development and its contents are subject to change. 03c0h 03c1h 03c2h 03c3h 03c4h 03c5h 03c6h 03c7h 03c8h 03c9h 03cah 03cbh 03cch 03cdh 03ceh 03cfh 03d0h 03d1h 03d2h 03d3h 03d4h 03d5h 03d6h 03d7h 03d8h 03d9h 03dah 03dbh 03dch 03ddh 03deh 03dfh 03e0h 03e1h 03e2h 03e3h 03e4h 03e5h 03e6h 03e7h 03e8h 03e9h 03eah 03ebh 03ech 03edh 03eeh 03efh 03f0h 03f1h 03f2h 03f3h 03f4h 03f5h 03f6h 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh a/d register 0 a/d register 1 a/d register 2 a/d register 3 a/d register 4 a/d register 5 a/d register 6 a/d register 7 a/d control register 2 a/d control register 0 a/d control register 1 d/a register 0 d/a register 1 d/a control register port p14 control register (2) pull-up control register 3 (2) port p0 register port p1 register port p0 direction register port p1 direction register port p2 register port p3 register port p2 direction register port p3 direction register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p9 register port p8 direction register port p9 direction register port p10 register port p11 register (2) port p10 direction register port p11 direction register (2) port p12 register (2) port p13 register (2) port p12 direction register (2) port p13 direction register (2) pull-up control register 0 pull-up control register 1 pull-up control register 2 port control register ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 adcon2 adcon0 adcon1 da0 da1 dacon pc14 pur3 p0 p1 pd0 pd1 p2 p3 pd2 pd3 p4 p5 pd4 pd5 p6 p7 pd6 pd7 p8 p9 pd8 pd9 p10 p11 pd10 pd11 p12 p13 pd12 pd13 pur0 pur1 pur2 pcr address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh 00h 00000xxxb 00h 00h 00h 00h xx00xxxxb 00h xxh xxh 00h 00h xxh xxh 00h 00h xxh xxh 00h 00h xxh xxh 00h 00h xxh xxh 00x00000b 00h xxh xxh 00h 00h xxh xxh 00h 00h 00h 00000000b (1) 00000010b 00h 00h x: undefined notes: 1. at hardware reset, the register is as follows: 00000000b where "l" is input to the cnvss pin 00000010b where "h" is input to the cnvss pin at software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: 00000000b where the pm01 to pm00 bits in the pm0 register are 00b (single-chip mode) 00000010b where the pm01 to pm00 bits in the pm0 register are 01b (memory expansion mode) or 11b (microprocessor mode) 2. these registers exist only in the128-pin version. 3. blank spaces are reserved. no access is allowed. table 4.12 sfr information (12) (3)
rev.2.10 aug 25, 2006 page 31 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. 5. electrical characteristics table 5.1 absolute maximum ratings note: 1. ports p11 to p14 are only in the 128-pin version. v cc av cc v i v o p d t opr t stg v v v v v v mw c c unit supply voltage (vcc1 = vcc2) analog supply voltage input voltage output voltage power dissipation operating ambient d uring mcu operation temperature during flash memory program and erase operation storage temperature symbol parameter _____________ reset, cnvss, byte, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, vref, xin p7_1, p9_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, xout p7_1, p9_1 rated value 0.3 to 6.5 0.3 to 6.5 0.3 to vcc+0.3 0.3 to 6.5 0.3 to vcc+0.3 0.3 to 6.5 700 40 to 85 0 to 60 65 to 150 condition vcc = avcc vcc = avcc topr = 25 c
rev.2.10 aug 25, 2006 page 32 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.2 recommended operating conditions (1) (1) supply voltage (vcc1 = vcc2) analog supply voltage supply voltage analog supply voltage high input voltage low input voltage high peak output current high average output current low peak output current low average output current p3_1 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, _____________ xin, reset, cnvss, byte p7_1, p9_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (during single-chip mode) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (data input during memory expansion and microprocessor modes) p3_1 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, _____________ p14_0, p14_1, xin, reset, cnvss, byte p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (during single-chip mode) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (data input during memory expansion and microprocessor modes) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 5.0 v cc 0 0 v v v v v v v v v v v ma ma ma ma 3.0 0.8 v cc 0.8 v cc 0.8 v cc 0.5 v cc 0 0 0 5.5 v cc 6.5 v cc v cc 0.2 v cc 0.2 v cc 0.16 v cc 10.0 5.0 10.0 5.0 v cc av cc v ss av ss v ih v il i oh(peak) i oh(avg) i ol(peak) i ol(avg) parameter symbol typ. min. standard unit max. notes: 1. referenced to vcc = 3.0 to 5.5 v at topr = 40 to 85 c unless otherwise specified. 2. average output current values during 100 ms period. 3. the total i ol(peak) for ports p0, p1, p2, p8_6, p8_7, p9, p10, p11, p14_0, and p14_1 must be 80 ma max. the total i ol(peak) for ports p3, p4, p5, p6, p7, p8_0 to p8_4, p12, and p13 must be 80 ma max. the total i oh(peak) for ports p0, p1, and p2 must be 40 ma max. the total i oh(peak) for ports p3, p4, p5, p12, and p13 must be 40 ma max. the total i oh(peak) for ports p6, p7, and p8_0 to p8_4 must be 40 ma max. the total i oh(peak) for ports p8_6, p8_7, p9, p10, p11, p14_0, and p14_1 must be 40 ma max. 4. p11 to p14 are only in the 128-pin version.
rev.2.10 aug 25, 2006 page 33 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.3 recommended operating conditions (2) (1) main clock input oscillation no wait mask rom version vcc = 3.0 to 5.5 v frequency (2) (3) (4) flash memory version sub clock oscillation frequency on-chip oscillation frequency pll clock oscillation frequency cpu operation clock vcc = 3.0 to 5.5 v pll frequency synthesizer stabilization wait time 32.768 1 mhz khz mhz mhz mhz ms 0 16 0 16 50 24 24 20 f(xin) f(xcin) f(ring) f(pll) f(bclk) t su(pll) parameter symbol typ. min. standard unit max. notes: 1. referenced to vcc = 3.0 to 5.5 v at topr = 40 to 85 c unless otherwise specified. 2. relationship between main clock oscillation frequency and supply voltage is shown right. 3. execute program/erase of flash memory by vcc = 3.3 0.3 v or vcc = 5.0 0.5 v. 4. when using 16 mhz and over, use pll clock. pll clock oscillation frequency which can be used is 16 mhz, 20 mhz or 24 mhz. 0.0 16.0 5.5 3.0 vcc [v] (main clock: no division) f(xin) operating maximum frequency [mhz] main clock input oscillation frequency (mask rom version / flash memory version: no wait)
rev.2.10 aug 25, 2006 page 34 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.4 electrical characteristics (1) (1) v cc -2.0 v cc -0.3 3.0 3.0 0.2 0.2 30 2.0 2.5 1.6 0 0 50 1.5 15 high output voltage high output voltage high output voltage high output voltage low output voltage low output voltage low output voltage low output voltage hysteresis hysteresis high input current low input current pull-up resistance feedback resistance feedback resistance ram retention voltage v oh v oh v oh v ol v ol v ol v t +-v t - v t +-v t - i ih i il r pullup r fxin r fxcin v ram i oh = 5 ma i oh = 200 a i oh = 1 ma i oh = 0.5 ma with no load applied with no load applied i ol = 5 ma i ol = 200 a i ol = 1 ma i ol = 0.5 ma with no load applied with no load applied v i = 5 v v i = 0 v v i = 0 v at stop mode v v v v v v v v v v a a k ? m ? m ? v measuring condition standard min. unit v cc v cc v cc v cc 2.0 0.45 2.0 2.0 1.0 2.5 5.0 5.0 170 parameter symbol p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xout highpower lowpower xcout highpower lowpower p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xout highpower lowpower xcout highpower lowpower __________ ________ hold, rdy, ta0in to ta4in, tb0in to tb5in, _________ _________ ________ ______________ __________ __________ int0 to int8, nmi, adtrg, cts0 to cts2, scl0 to scl2, sda0 to sda2, clk0 to clk6, ______ ______ ta0out to ta4out, ki0 to ki3, rxd0 to rxd2, sin3 to sin6 _____________ reset p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, ____________ xin, reset, cnvss, byte p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, ____________ xin, reset, cnvss, byte p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xin xcin typ. max. notes: 1. referenced to vcc = 4.2 to 5.5 v, vss = 0 v at topr = 40 to 85 c, f(bclk) = 24 mhz unless otherwise specified. ________ ________ 2. p11 to p14, int6 to int8, clk5, clk6, sin5, and sin6 are only in the 128-pin version. vcc = 5v
rev.2.10 aug 25, 2006 page 35 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.5 electrical characteristics (2) (1) mask rom f(bclk) = 24 mhz, pll operation, no division on-chip oscillation, no division flash memory f(bclk) = 24 mhz, pll operation, no division on-chip oscillation, no division flash memory f(bclk) = 10 mhz, program vcc = 5 v flash memory f(bclk) = 10 mhz, erase vcc = 5 v mask rom f(bclk) = 32 khz, low power dissipation mode, rom (2) flash memory f(bclk) = 32 khz, low power dissipation mode, ram (2) f(bclk) = 32 khz, low power dissipation mode, flash memory (2) mask rom on-chip oscillation, flash memory wait mode f(bclk) = 32 khz, wait mode (3) , oscillation capacity high f(bclk) = 32 khz, wait mode (3) , oscillation capacity low stop mode, topr = 25 c notes: 1. referenced to vcc = 3.0 to 5.5 v, vss = 0 v at topr = 40 to 85 c, f(bclk) = 24 mhz unless otherwise specified. 2. this indicates the memory in which the program to be executed exists. 3. with one timer operated using fc32. 19 1 21 1.8 15 25 25 25 420 50 8.5 3.0 0.8 power supply current (vcc = 3.0 to 5.5 v) i cc ma ma ma ma ma ma a a a a a a a measuring condition standard min. unit 33 35 3.0 parameter symbol in single-chip mode, the output pins are open and other pins are vss. typ. max.
rev.2.10 aug 25, 2006 page 36 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.6 a/d conversion characteristics (1) 10 3 7 5 7 2 3 7 5 7 2 1 3 3 40 v cc v ref bit lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb lsb k ? s s s v v 10 3.3 2.8 0.3 2.0 0 vref = vcc vref = vcc = 5 v vref = vcc = 3.3 v vref = avcc = vcc = 3.3 v vref = vcc = 5 v vref = vcc = 3.3 v vref = avcc = vcc = 3.3 v vref = vcc vref = vcc = 5 v, ad = 10 mhz vref = vcc = 5 v, ad = 10 mhz anex0, anex1 input, an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input external operation amp connection mode anex0, anex1 input, an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input external operation amp connection mode anex0, anex1 input, an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input external operation amp connection mode anex0, anex1 input, an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input external operation amp connection mode resolution integral 10 bits nonlinearity error 8 bits absolute 10 bits accuracy 8 bits differential nonlinearity error offset error gain error resistor ladder 10-bit conversion time, sample & hold available 8-bit conversion time, sample & hold available sampling time reference voltage analog input voltage inl dnl r ladder t conv t samp v ref v ia symbol parameter min. standard unit measuring condition max. typ. (note 2) 8 1.0 3 20 1.5 bits % s k ? ma resolution absolute accuracy setup time output resistance reference power supply input current t su r o i vref symbol parameter min. standard unit measuring condition 4 max. typ. 10 notes: 1. referenced to vcc = avcc = vref = 3.3 to 5.5 v, vss = avss = 0 v, 40 to 85 c unless otherwise specified. 2. ad frequency must be 10 mhz or less. 3. when sample & hold is disabled, ad frequency must be 250 khz or more in addition to a limit of note 2. when sample & hold is enabled, ad frequency must be 1 mhz or more in addition to a limit of note 2. table 5.7 d/a conversion characteristics (1) notes: 1. referenced to vcc = avcc = vref = 3.3 to 5.5 v, vss = avss = 0 v, 40 to 85 c unless otherwise specified. 2. this applies when using one d/a converter, with the dai register (i = 0, 1) for the unused d/a converter set to 00h. the resistor ladder of the a/d converter is not included. also, the i vref will flow even if vref is disconnected by the adcon1 register.
rev.2.10 aug 25, 2006 page 37 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. 2 150 150 ms s s time for internal power supply stabilization during powering-on stop release time low power dissipation mode wait mode release time t d(p-r) t d(r-s) t d(w-s) symbol parameter min. standard unit measuring condition max. typ. vcc = 3.0 to 5.5 v table 5.10 power supply circuit timing ch aracteristics cpu clock vcc t d(p-r) t d(p-r) time for internal power supply stabilization during powering-on t d(r-s) stop release time t d(w-s) low power dissipation mode wait mode release time cpu clock t d(w-s) t d(r-s) (b) (a) interrupt for (a) stop mode release or (b) wait mode release figure 5.1 power supply circuit timing diagram vcc = 3.3 0.3 v or 5.0 0.5 v flash read operation voltage flash program, erase voltage vcc = 3.0 to 5.5 v table 5.8 flash memory version electrical characteristics (1) notes: 1. referenced to vcc = 4.5 to 5.5 v, 3.0 to 3.6 v, topr = 0 to 60 c unless otherwise specified. 2. programming and erasure endurance refers to the number of times a block erase can be performed. if the programming and erasure endurance is n (n = 100), each block can be erased n times. for example, if a 4-kbyte block a is erased after writing 1 word data 2,048 times, each to a different address, this counts as one programming and erasure endurance. data cannot be written to the same address more than once without erasing the block (rewrite prohibited). 3. n denotes the number of blocks to erase. table 5.9 flash memory version program/erase voltage and read operation voltage characteristics (at topr = 0 to 60?) 200 200 4 4 4 4 4 ? n (3) 15 cycle s s s s s s s s programming and erasure endurance (2) word program time (vcc = 5.0 v) lock bit program time block erase time 4-kbyte block (vcc = 5.0 v) 8-kbyte block 32-kbyte block 64-kbyte block erase all unlocked blocks time flash memory circuit stabilization wait time parameter min. standard unit max. typ. 25 25 0.3 0.3 0.5 0.8 symbol - - - - - tps 100
rev.2.10 aug 25, 2006 page 38 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. 15 15 ns ns ns ns ns external clock input cycle time external clock input high pulse width external clock input low pulse width external clock rise time external clock fall time symbol parameter min. standard unit max. 62.5 25 25 t c t w(h) t w(l) t r t f timing requirements (referenced to vcc = 5 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.11 external clock input (xin input) table 5.12 memory expansion mode and microprocessor mode (note 1) (note 2) (note 3) ns ns ns ns ns ns ns ns ns data input access time (for setting with no wait) data input access time (for setting with wait) data input access time (when accessing multiplexed bus area) data input setup time ________ rdy input setup time __________ hold input setup time data input hold time ________ rdy input hold time __________ hold input hold time symbol parameter min. standard unit max. 40 30 40 0 0 0 t ac1(rd-db) t ac2(rd-db) t ac3(rd-db) t su(db-rd) t su(rdy-bclk) t su(hold-bclk) t h(rd-db) t h(bclk-rdy) t h(bclk-hold) notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 45 [ns] 2. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 f(bclk) 45 [ns] n is 2 for 1-wait setting, 3 for 2-wait setting and 4 for 3-wait setting. 3. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 f(bclk) 45 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. vcc = 5 v
rev.2.10 aug 25, 2006 page 39 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. timing requirements (referenced to vcc = 5 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.13 timer a input (counter input in event counter mode) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 100 40 40 table 5.14 timer a input (gating input in timer mode) t c(ta) t w(tah) t w(tal) table 5.15 timer a input (external trigger input in one-shot timer mode) table 5.16 timer a input (external trigger input in pulse width modulation mode) table 5.17 timer a input (counter increment/decrement input in event counter mode) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 400 200 200 t c(ta) t w(tah) t w(tal) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 200 100 100 t c(ta) t w(tah) t w(tal) ns ns taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 100 100 t w(tah) t w(tal) ns ns ns ns ns taiout input cycle time taiout input high pulse width taiout input low pulse width taiout input setup time taiout input hold time symbol parameter min. standard unit max. 2000 1000 1000 400 400 t c(up) t w(uph) t w(upl) t su(up-tin) t h(tin-up) table 5.18 timer a input (two-phase pulse input in event counter mode) ns ns ns taiin input cycle time taiout input setup time taiin input setup time symbol parameter min. standard unit max. 800 200 200 t c(ta) t su(tain-taout) t su(taout-tain) vcc = 5 v
rev.2.10 aug 25, 2006 page 40 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. ns ns ns ns ns ns tbiin input cycle time (counted on one edge) tbiin input high pulse width (counted on one edge) tbiin input low pulse width (counted on one edge) tbiin input cycle time (counted on both edges) tbiin input high pulse width (counted on both edges) tbiin input low pulse width (counted on both edges) symbol parameter min. standard unit max. 100 40 40 200 80 80 table 5.20 timer b input (pulse period measurement mode) t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timing requirements (referenced to vcc = 5 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.19 timer b input (counter input in event counter mode) table 5.21 timer b input (pulse width measurement mode) table 5.22 a/d trigger input table 5.23 serial interface ns ns ns tbiin input cycle time tbiin input high pulse width tbiin input low pulse width symbol parameter min. standard unit max. 400 200 200 t c(tb) t w(tbh) t w(tbl) ns ns ns tbiin input cycle time tbiin input high pulse width tbiin input low pulse width symbol parameter min. standard unit max. 400 200 200 t c(tb) t w(tbh) t w(tbl) ns ns _____________ adtrg input cycle time (trigger able minimum) _____________ adtrg input low pulse width symbol parameter min. standard unit max. 1000 125 t c(ad) t w(adl) 80 ns ns ns ns ns ns ns clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time symbol parameter min. standard unit max. 200 100 100 0 70 90 t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) _______ table 5.24 external interrupt inti input ns ns _______ inti input high pulse width _______ inti input low pulse width symbol parameter min. standard unit max. 250 250 t w(inh) t w(inl) vcc = 5 v
rev.2.10 aug 25, 2006 page 41 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (in relation to bclk) address output hold time (in relation to rd) address output hold time (in relation to wr) chip select output delay time chip select output hold time (rin relation to bclk) ale signal output delay time ale signal output hold time rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (in relation to bclk) data output hold time (in relation to bclk) (3) data output delay time (in relation to wr) data output hold time (rin relation to wr) (3) __________ hlda output delay time symbol parameter min. standard unit max. 4 0 (note 1) 4 4 0 0 4 (note 2) (note 1) switching characteristics (referenced to vcc = 5 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.25 memory expansion mode and microprocessor mode (for setting with no wait) 25 25 15 25 25 40 40 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 10 [ns] 2. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 40 [ns] 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = cr ? ln (1 v ol / v cc ) by a circuit of the right figure. for example, when v ol = 0.2 v cc , c = 30 pf, r =1 k ? , hold time of output l level is t = 30 pf ? 1 k ? ? ln (1 0.2 v cc / v cc ) = 6.7 ns. figure 5.2 port p0 to p14 measurement circuit dbi r c 30 pf p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 note: 1. p11 to p14 are only in the 128-pin version. measuring condition figure 5.2 f(bclk) is 12.5 mhz or less. vcc = 5 v
rev.2.10 aug 25, 2006 page 42 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (in relation to bclk) address output hold time (in relation to rd) address output hold time (in relation to wr) chip select output delay time chip select output hold time (in relation to bclk) ale signal output delay time ale signal output hold time rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (in relation to bclk) data output hold time (rin relation to bclk) (3) data output delay time (in relation to wr) data output hold time (in relation to wr) (3) __________ hlda output delay time symbol parameter min. standard unit max. 4 0 (note 1) 4 4 0 0 4 (note 2) (note 1) switching characteristics (referenced to vcc = 5 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.26 memory expansion mode and microprocessor mode (for 1- to 3-wait setting and external area access) 25 25 15 25 25 40 40 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 10 [ns] 2. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 n is 1 for 1-wait setting, 2 for 2-wait setting and 3 for 3-wait setting. f(bclk) 40 [ns] when n = 1, f(bclk) is 12.5 mhz or less. 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = cr ? ln (1 v ol / v cc ) by a circuit of the right figure. for example, when v ol = 0.2 v cc , c = 30 pf, r =1 k ? , hold time of output l level is t = 30 pf ? 1 k ? ? ln (1 0.2 v cc / v cc ) = 6.7 ns. dbi r c measuring condition figure 5.2 vcc = 5 v
rev.2.10 aug 25, 2006 page 43 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. 4 (note 1) (note 1) 4 (note 1) (note 1) 0 0 4 (note 2) (note 1) 4 (note 3) (note 4) 0 0 t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t h(rd-cs) t h(wr-cs) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) t d(bclk-ale) t h(bclk-ale) t d(ad-ale) t h(ale-ad) t d(ad-rd) t d(ad-wr) t dz(rd-ad) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (in relation to bclk) address output hold time (in relation to rd) address output hold time (in relation to wr) chip select output delay time chip select output hold time (in relation to bclk) chip select output hold time (in relation to rd) chip select output hold time (in relation to wr) rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (in relation to bclk) data output hold time (in relation to bclk) data output delay time (in relation to wr) data output hold time (in relation to wr) __________ hlda output delay time ale signal output delay time (in relation to bclk) ale signal output hold time (in relation to bclk) ale signal output delay time (in relation to address) ale signal output hold time (in relation to address) rd signal output delay from the end of address wr signal output delay from the end of address address output floating start time symbol parameter min. standard unit max. switching characteristics (referenced to vcc = 5 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.27 memory expansion mode and microprocessor mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) 25 25 25 25 40 40 15 8 measuring condition figure 5.2 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 10 [ns] 2. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 f(bclk) 40 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. 3. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 25 [ns] 4. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 15 [ns] vcc = 5 v
rev.2.10 aug 25, 2006 page 44 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.3 timing diagram (1) t su(d c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c q) t h(c d) t h(c q) inti input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) adtrg input tbiin input two-phase pulse input in event counter mode t su(taout tain) t su(taout tain) t su(tain taout) t c(ta) t su(tain taout) taiin input taiout input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) taiin input taiout input during event counter mode taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) t h(tin up) t su(up tin) t r t r t c t w(h) t w(l) xin input vcc = 5 v
rev.2.10 aug 25, 2006 page 45 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.4 timing diagram (2) measuring conditions : vcc = 5 v input timing voltage : determined with v il = 1.0 v, v ih = 4.0 v output timing voltage: determined with v ol = 2.5 v, v oh = 2.5 v bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 (1) note: 1. the above pins are set to high-impedance regardless of the input level of the byte pin, the pm06 bit in the pm0 register, and the pm11 bit in the pm1 register. hi z rdy input bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) t d(bclk hlda) t d(bclk hlda) t h(bclk hold) t su(hold bclk) tsu(rdy bclk) th(bclk rdy) memory expansion mode and microprocessor mode (effective for setting with wait) (common to setting with wait and setting without wait) vcc = 5 v
rev.2.10 aug 25, 2006 page 46 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.5 timing diagram (3) bclk csi t d(bclk-cs) 25ns.max adi 25ns.max ale 25ns.max -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe tcyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 40ns.min t ac1(rd-db) memory expansion mode and microprocessor mode (for setting with no wait) wr,wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 ? tcyc-40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 ? tcyc-45)ns.max (0.5 ? tcyc-10)ns.min tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v (0.5 ? tcyc-10)ns.min vcc = 5 v
rev.2.10 aug 25, 2006 page 47 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.6 timing diagram (4) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t su(db-rd) 40ns.min t h(rd-db) 0ns.min tcyc bhe read timing wr,wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 ? tcyc-40)ns.min (0.5 ? tcyc-10)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode and microprocessor mode (for 1-wait setting and external area access) (1.5 ? tcyc-45)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v (0.5 ? tcyc-10)ns.min vcc = 5 v
rev.2.10 aug 25, 2006 page 48 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.7 timing diagram (5) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode and microprocessor mode (for 2-wait setting and external area access) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 ? tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min t ac2(rd-db) (2.5 ? tcyc-45)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v vcc = 5 v
rev.2.10 aug 25, 2006 page 49 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.8 timing diagram (6) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode and microprocessor mode (for 3-wait setting and external area access) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 ? tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min t ac2(rd-db) (3.5 ? tcyc-45)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v vcc = 5 v
rev.2.10 aug 25, 2006 page 50 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.9 timing diagram (7) memory expansion mode and microprocessor mode (for 1- or 2-wait setting, external area access and multiplexed bus selection) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address address data input 40ns.min (0.5 ? tcyc-10)ns.min t d(bclk-ale) t d(bclk-rd) t h(wr-cs) address t d(ad-ale) (0.5 ? tcyc-25)ns.min (1.5 ? tcyc-40)ns.min (0.5 ? tcyc-10)ns.min t d(bclk-ale) (0.5 ? tcyc-25)ns.min address 25ns.max t su(db-rd) t ac3(rd-db) (0.5 ? tcyc-10)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min t h(ale-ad) tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v (1.5 ? tcyc-45)ns.max (0.5 ? tcyc-10)ns.min (0.5 ? tcyc-10)ns.min (0.5 ? tcyc-15)ns.min vcc = 5 v
rev.2.10 aug 25, 2006 page 51 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.10 timing diagram (8) read timing write timing memory expansion mode and microprocessor mode (for 3-wait setting, external area access and multiplexed bus selection) bclk csi ale rd adi /dbi adi bhe bclk csi ale adi /dbi tcyc t d(bclk-ad) 25ns.max tcyc data output t h(bclk-cs) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max t h(bclk-rd) 0ns.min t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 ? tcyc-10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 25ns.max t d(bclk-wr) 25ns.max t -4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min data input address address adi bhe wr, wrl wrh t d(ad-ale) (0.5 ? tcyc-25)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 40ns.max (0.5 ? tcyc-10)ns.min t h(wr-cs) t d(ad-wr) 0ns.min t h(rd-cs) (0.5 ? tcyc-10)ns.min t d(ad-ale) (0.5 ? tcyc-25)ns.min (2.5 ? tcyc-45)ns.max (no multiplex) (no multiplex) tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v t d(db-wr) (2.5 ? tcyc-40)ns.min h(bclk-ale) (0.5 ? tcyc-15)ns.min t h(ale-ad) vcc = 5 v
rev.2.10 aug 25, 2006 page 52 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.28 electrical characteristics (1) v cc -0.5 v cc -0.5 v cc -0.5 0.2 0.2 50 2.0 2.5 1.6 0 0 100 3.0 25 high output voltage high output voltage high output voltage low output voltage low output voltage low output voltage hysteresis hysteresis high input current low input current pull-up resistance feedback resistance feedback resistance ram retention voltage v oh v oh v ol v ol v t +-v t - v t +-v t - i ih i il r pullup r fxin r fxcin v ram i oh = 1 ma i oh = 0.1 ma i oh = 50 a with no load applied with no load applied i ol = 1 ma i ol = 0.1 ma i ol = 50 a with no load applied with no load applied v i = 3.3 v v i = 0 v v i = 0 v at stop mode v v v v v v v v a a k ? m ? m ? v measuring condition standard min. unit v cc v cc v cc 0.5 0.5 0.5 0.8 1.8 4.0 4.0 500 parameter symbol p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7,p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xout highpower lowpower xcout highpower lowpower p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7,p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xout highpower lowpower xcout highpower lowpower _________ _______ hold, rdy, ta0in to ta4in, tb0in to tb5in, ________ ________ _______ _____________ _________ _________ int0 to int8, nmi, adtrg, cts0 to cts2, scl0 to scl2, sda0 to sda2, clk0 to clk6, _____ _____ ta0out to ta4out, ki0 to ki3, rxd0 to rxd2, sin3 to sin6 _____________ reset p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, ____________ xin, reset, cnvss, byte p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1, ____________ xin, reset, cnvss, byte p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, p11_0 to p11_7, p12_0 to p12_7, p13_0 to p13_7, p14_0, p14_1 xin xcin typ. max. notes: 1. referenced to vcc = 3.0 to 3.6 v, vss = 0 v at topr = 40 to 85 c, f(bclk) = 24 mhz unless otherwise specified. ________ ________ 2. p11 to p14, int6 to int8, clk5, clk6, sin5, and sin6 are only in the 128-pin version. vcc = 3.3 v
rev.2.10 aug 25, 2006 page 53 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. 15 15 ns ns ns ns ns external clock input cycle time external clock input high pulse width external clock input low pulse width external clock rise time external clock fall time symbol parameter min. standard unit max. 62.5 25 25 t c t w(h) t w(l) t r t f timing requirements (referenced to vcc = 3.3 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.29 external clock input (xin input) table 5.30 memory expansion mode and microprocessor mode (note 1) (note 2) (note 3) ns ns ns ns ns ns ns ns ns data input access time (for setting with no wait) data input access time (for setting with wait) data input access time (when accessing multiplexed bus area) data input setup time ________ rdy input setup time __________ hold input setup time data input hold time ________ rdy input hold time __________ hold input hold time symbol parameter min. standard unit max. 50 40 50 0 0 0 t ac1(rd-db) t ac2(rd-db) t ac3(rd-db) t su(db-rd) t su(rdy-bclk) t su(hold-bclk) t h(rd-db) t h(bclk-rdy) t h(bclk-hold) notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 60 [ns] 2. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 f(bclk) 60 [ns] n is 2 for 1-wait setting, 3 for 2-wait setting and 4 for 3-wait setting. 3. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 f(bclk) 60 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. vcc = 3.3 v
rev.2.10 aug 25, 2006 page 54 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. timing requirements (referenced to vcc = 3.3 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.31 timer a input (counter input in event counter mode) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 150 60 60 table 5.32 timer a input (gating input in timer mode) t c(ta) t w(tah) t w(tal) table 5.33 timer a input (external trigger input in one-shot timer mode) table 5.34 timer a input (external trigger input in pulse width modulation mode) table 5.35 timer a input (counter increment/decrement input in event counter mode) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 600 300 300 t c(ta) t w(tah) t w(tal) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 300 150 150 t c(ta) t w(tah) t w(tal) ns ns taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 150 150 t w(tah) t w(tal) ns ns ns ns ns taiout input cycle time taiout input high pulse width taiout input low pulse width taiout input setup time taiout input hold time symbol parameter min. standard unit max. 3000 1500 1500 600 600 t c(up) t w(uph) t w(upl) t su(up-tin) t h(tin-up) table 5.36 timer a input (two-phase pulse input in event counter mode) s ns ns taiin input cycle time taiout input setup time taiin input setup time symbol parameter min. standard unit max. 2 500 500 t c(ta) t su(tain-taout) t su(taout-tain) vcc = 3.3 v
rev.2.10 aug 25, 2006 page 55 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. ns ns ns ns ns ns tbiin input cycle time (counted on one edge) tbiin input high pulse width (counted on one edge) tbiin input low pulse width (counted on one edge) tbiin input cycle time (counted on both edges) tbiin input high pulse width (counted on both edges) tbiin input low pulse width (counted on both edges) symbol parameter min. standard unit max. 150 60 60 300 120 120 table 5.38 timer b input (pulse period measurement mode) t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timing requirements (referenced to vcc = 3.3 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.37 timer b input (counter input in event counter mode) table 5.39 timer b input (pulse width measurement mode) table 5.40 a/d trigger input table 5.41 serial interface ns ns ns tbiin input cycle time tbiin input high pulse width tbiin input low pulse width symbol parameter min. standard unit max. 600 300 300 t c(tb) t w(tbh) t w(tbl) ns ns ns tbiin input cycle time tbiin input high pulse width tbiin input low pulse width symbol parameter min. standard unit max. 600 300 300 t c(tb) t w(tbh) t w(tbl) ns ns _____________ adtrg input cycle time (trigger able minimum) _____________ adtrg input low pulse width symbol parameter min. standard unit max. 1500 200 t c(ad) t w(adl) 160 ns ns ns ns ns ns ns clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time symbol parameter min. standard unit max. 300 150 150 0 100 90 t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) _______ table 5.42 external interrupt inti input ns ns _______ inti input high pulse width _______ inti input low pulse width symbol parameter min. standard unit max. 380 380 t w(inh) t w(inl) vcc = 3.3 v
rev.2.10 aug 25, 2006 page 56 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (in relation to bclk) address output hold time (in relation to rd) address output hold time (in relation to wr) chip select output delay time chip select output hold time (in relation to bclk) ale signal output delay time ale signal output hold time rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (in relation to bclk) data output hold time (in relation to bclk) (3) data output delay time (in relation to wr) data output hold time (in relation to wr) (3) __________ hlda output delay time symbol parameter min. standard unit max. 4 0 (note 1) 4 4 0 0 4 (note 2) (note 1) switching characteristics (referenced to vcc = 3.3 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.43 memory expansion mode and microprocessor mode (for setting with no wait) 30 30 25 30 30 40 40 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 10 [ns] 2. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 40 [ns] 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = cr ? ln (1 v ol / v cc ) by a circuit of the right figure. for example, when v ol = 0.2 v cc , c = 30 pf, r =1 k ? , hold time of output l level is t = 30 pf ? 1 k ? ? ln (1 0.2 v cc / v cc ) = 6.7 ns. figure 5.11 port p0 to p14 measurement circuit dbi r c 30 pf p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 note: 1. p11 to p14 are only in the 128-pin version. measuring condition figure 5.11 f(bclk) is 12.5 mhz or less. vcc = 3.3 v
rev.2.10 aug 25, 2006 page 57 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (in relation to bclk) address output hold time (in relation to rd) address output hold time (in relation to wr) chip select output delay time chip select output hold time (in relation to bclk) ale signal output delay time ale signal output hold time rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (in relation to bclk) data output hold time (in relation to bclk) (3) data output delay time (in relation to wr) data output hold time (in relation to wr) (3) __________ hlda output delay time symbol parameter min. standard unit max. 4 0 (note 1) 4 4 0 0 4 (note 2) (note 1) switching characteristics (referenced to vcc = 3.3 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.44 memory expansion mode and microprocessor mode (for 1- to 3-wait setting and external area access) 30 30 25 30 30 40 40 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 10 [ns] 2. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 n is 1 for 1-wait setting, 2 for 2-wait setting and 3 for 3-wait setting. f(bclk) 40 [ns] when n = 1, f(bclk) is 12.5 mhz or less. 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = cr ? ln (1 v ol / v cc ) by a circuit of the right figure. for example, when v ol = 0.2 v cc , c = 30 pf, r =1 k ? , hold time of output l level is t = 30 pf ? 1 k ? ? ln (1 0.2 v cc / v cc ) = 6.7 ns. dbi r c measuring condition figure 5.11 vcc = 3.3 v
rev.2.10 aug 25, 2006 page 58 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. 4 (note 1) (note 1) 4 (note 1) (note 1) 0 0 4 (note 2) (note 1) 4 (note 3) (note 4) 0 0 t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t h(rd-cs) t h(wr-cs) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) t d(bclk-ale) t h(bclk-ale) t d(ad-ale) t h(ale-ad) t d(ad-rd) t d(ad-wr) t dz(rd-ad) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (in relation to bclk) address output hold time (in relation to rd) address output hold time (in relation to wr) chip select output delay time chip select output hold time (in relation to bclk) chip select output hold time (in relation to rd) chip select output hold time (in relation to wr) rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (in relation to bclk) data output hold time (in relation to bclk) data output delay time (in relation to wr) data output hold time (in relation to wr) __________ hlda output delay time ale signal output delay time (in relation to bclk) ale signal output hold time (in relation to bclk) ale signal output delay time (in relation to address) ale signal output hold time (rin relation to address) rd signal output delay from the end of address wr signal output delay from the end of address address output floating start time symbol parameter min. standard unit max. switching characteristics (referenced to vcc = 3.3 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.45 memory expansion mode and microprocessor mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) 50 50 40 40 50 40 25 8 measuring condition figure 5.11 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 10 [ns] 2. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 f(bclk) 50 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. 3. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 40 [ns] 4. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 15 [ns] vcc = 3.3 v
rev.2.10 aug 25, 2006 page 59 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.12 timing diagram (1) t su(d c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c q) t h(c d) t h(c q) inti input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) adtrg input tbiin input two-phase pulse input in event counter mode t su(taout tain) t su(taout tain) t su(tain taout) t c(ta) t su(tain taout) taiin input taiout input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) taiin input taiout input during event counter mode taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) t h(tin up) t su(up tin) t r t r t c t w(h) t w(l) xin input vcc = 3.3 v
rev.2.10 aug 25, 2006 page 60 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.13 timing diagram (2) measuring conditions : vcc = 3.3 v input timing voltage : determined with v il = 0.6 v, v ih = 2.7 v output timing voltage: determined with v ol = 1.65 v, v oh = 1.65 v bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 (1) note: 1. the above pins are set to high-impedance regardless of the input level of the byte pin, the pm06 bit in the pm0 register, and the pm11 bit in the pm1 register. hi z rdy input bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) t d(bclk hlda) t d(bclk hlda) t h(bclk hold) t su(hold bclk) tsu(rdy bclk) th(bclk rdy) memory expansion mode and microprocessor mode (effective for setting with wait) (common to setting with wait and setting without wait) vcc = 3.3 v
rev.2.10 aug 25, 2006 page 61 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.14 timing diagram (3) bclk csi t d(bclk-cs) 30ns.max adi 30ns.max ale 30ns.max -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe tcyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 50ns.min t ac1(rd-db) memory expansion mode and microprocessor mode (for setting with no wait) wr,wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 ? tcyc-40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 ? tcyc-60)ns.max (0.5 ? tcyc-10)ns.min tcyc = 1 f(bclk) measuring conditions : vcc = 3.3 v input timing voltage : v il = 0.6 v, v ih = 2.7 v output timing voltage : v ol = 1.65 v, v oh = 1.65 v (0.5 ? tcyc-10)ns.min vcc = 3.3 v
rev.2.10 aug 25, 2006 page 62 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.15 timing diagram (4) bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t h(bclk-ale) -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t su(db-rd) 50ns.min t h(rd-db) 0ns.min tcyc bhe read timing wr,wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 ? tcyc-40)ns.min (0.5 ? tcyc-10)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode and microprocessor mode (for 1-wait setting and external area access) (1.5 ? tcyc-60)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 3.3 v input timing voltage : v il = 0.6 v, v ih = 2.7 v output timing voltage : v ol = 1.65 v, v oh = 1.65 v (0.5 ? tcyc-10)ns.min vcc = 3.3 v
rev.2.10 aug 25, 2006 page 63 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.16 timing diagram (5) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode and microprocessor mode (for 2-wait setting and external area access) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 ? tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min t ac2(rd-db) (2.5 ? tcyc-60)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 3.3 v input timing voltage : v il = 0.6 v, v ih = 2.7 v output timing voltage : v ol = 1.65 v, v oh = 1.65 v vcc = 3.3 v
rev.2.10 aug 25, 2006 page 64 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.17 timing diagram (6) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode and microprocessor mode (for 3-wait setting and external area access) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 30ns.max hi-z t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 30ns.max t d(bclk-ad) 30ns.max t d(bclk-ale) 30ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 30ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 ? tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min t ac2(rd-db) (3.5 ? tcyc-60)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 3.3 v input timing voltage : v il = 0.6 v, v ih = 2.7 v output timing voltage : v ol = 1.65 v, v oh = 1.65 v vcc = 3.3 v
rev.2.10 aug 25, 2006 page 65 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.18 timing diagram (7) memory expansion mode and microprocessor mode (for 2-wait setting, external area access and multiplexed bus selection) bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale t h(bclk-ale) -4ns.min rd 40ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 40ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 40ns.max adi t d(bclk-ad) 40ns.max ale 40ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 50ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address address data input 50ns.min (0.5 ? tcyc-10)ns.min t d(bclk-ale) t d(bclk-rd) t h(wr-cs) address t d(ad-ale) (0.5 ? tcyc-40)ns.min (1.5 ? tcyc-50)ns.min (0.5 ? tcyc-10)ns.min t d(bclk-ale) (0.5 ? tcyc-40)ns.min address 40ns.max t su(db-rd) t ac3(rd-db) (0.5 ? tcyc-10)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min t h(ale-ad) tcyc = 1 f(bclk) measuring conditions : vcc = 3.3 v input timing voltage : v il = 0.6 v, v ih = 2.7 v output timing voltage : v ol = 1.65 v, v oh = 1.65 v (1.5 ? tcyc-60)ns.max (0.5 ? tcyc-10)ns.min (0.5 ? tcyc-10)ns.min (0.5 ? tcyc-15)ns.min vcc = 3.3 v
rev.2.10 aug 25, 2006 page 66 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.19 timing diagram (8) read timing write timing memory expansion mode and microprocessor mode (for 3-wait setting, external area access and multiplexed bus selection) bclk csi ale rd adi /dbi adi bhe bclk csi ale adi /dbi tcyc t d(bclk-ad) 40ns.max tcyc data output t h(bclk-cs) 6ns.min t d(bclk-cs) 40ns.max t d(bclk-ale) 40ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 40ns.max t h(bclk-rd) 0ns.min t su(db-rd) 50ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 ? tcyc-10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 40ns.max t d(bclk-ad) 40ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 40ns.max t d(bclk-wr) 40ns.max t -4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min data input address address adi bhe wr, wrl wrh t d(ad-ale) (0.5 ? tcyc-40)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 50ns.max (0.5 ? tcyc-10)ns.min t h(wr-cs) t d(ad-wr) 0ns.min t h(rd-cs) (0.5 ? tcyc-10)ns.min t d(ad-ale) (0.5 ? tcyc-40)ns.min (2.5 ? tcyc-60)ns.max (no multiplex) (no multiplex) tcyc = 1 f(bclk) measuring conditions : vcc = 3.3 v input timing voltage : v il = 0.6 v, v ih = 2.7 v output timing voltage : v ol = 1.65 v, v oh = 1.65 v t d(db-wr) (2.5 ? tcyc-50)ns.min h(bclk-ale) (0.5 ? tcyc-15)ns.min t h(ale-ad) vcc = 3.3 v
rev.2.10 aug 25, 2006 page 67 of 67 rej03b0061-0210 m16c/6n group (m16c/6nl, m16c/6nn) appendix 1. package dimensions under development this document is under development and its contents are subject to change. appendix 1. package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. detailf l 1 c a a 1 a 2 l index mark y x f 1 38 39 64 65 102 103 128 * 1 * 3 * 2 z e z d d h d e h e b p l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.10 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.125 0.2 a 1.7 15.8 16.0 16.2 21.8 22.0 22.2 a 2 1.4 e 13.9 14.0 14.1 d 19.9 20.0 20.1 reference symbol dimension in millimeters min nom max 0.17 0.22 0.27 0.09 0.145 0.20 0.10 0.75 0.75 0.20 0.125 1.0 p-lqfp128-14x20-0.50 0.9g mass[typ.] 128p6q-a plqp0128kb-a renesas code jeita package code previous code terminal cross section c bp c 1 b 1 e
revision history m16c/6n group (m16c/6nl, m16c/6nn) data sheet rev. date description page summary a-1 1.00 jul. 20, 2004 1.01 nov. 01, 2004 1.02 jul. 01, 2005 2.10 aug.25, 2006 first edition issued revised edition issued * revised parts and revised contents are as follows (except for expressional change). 26 table 5.2 recommended operating conditions (1) i oh(peak) : unit is revised from ??to ?a? 27 table 5.3 recommended operating conditions (2) note 3: vcc = 3.0 ?0.3 v is revised to vcc = 3.3 ?0.3 v. 28 table 5.4 i ih , i il : ?3_3?is revised to ?3_7?in parameter. 31 table 5.9: vcc = 3.0 ?0.3 v?is revised to ?cc = 3.3 ?0.3 v?in flash program, erase voltage. revised edition issued * revised parts and revised contents are as follows (except for expressional change). 5 table 1.3 product list is revised. 13 figure 4.1 sfr information (1): the value of after reset in cm2 register is revised. 19 figure 4.7 sfr information (7): note 1 is revised. 28 table 5.4 electrical characteristics (1) ?measuring condition of v ol is revised from ? ol = ?00??to ? ol = 200?. 29 table 5.5 electrical characteristics (2): mask rom (5th item) ??(xcin)?is changed to ?f(bclk)). 30 table 5.6 a/d conversion characteristics: ?olerance level impedance?is deleted. revised edition issued * memory expansion and microprocessor modes are added. * revised parts and revised contents are as follows (except for expressional change). 2 table 1.1 fuictions and specifications for m16c/6n group (100-pin version) ?operating mode is revised. 3 table 1.2 fuictions and specifications for m16c/6n group (128-pin version) ?operating mode is revised. 5 table 1.3 product information ?status of development is revised and notes 1 and 2 are added. 6 figure 1.3 pin assignments (1): bus control pins are added. 7, 8 tables 1.4 and 1.5 list of pin names for 100-pin package (1)(2) are added. 9 figure 1.4 pin assignments (2): bus control pins are added. 10 to 12 tables 1.6 to 1.8 list of pin names for 128-pin package (1)(2)(3) are added. 13 to 15 tables 1.9 to 1.11 pin functions (1)(2)(3) are revised. 18 3. memory: last sentence (in memory expansion ...) is added. figure 3.1 memory map: notes 1 and 2 are added. 19 table 4.1 sfr information (1) ?value of after reset in pm0 is revised. ?csr register is added to 0008h. cse register is added to 001bh. ?note 1 is added.
revision history m16c/6n group (m16c/6nl, m16c/6nn) data sheet rev. date description page summary a-2 26 table 4.8 sfr information (8) ?the value of after reset in idb0 register is revised. ?the value of after reset in idb1 register is revised. 30 table 4.12 sfr information (12) ?value of after reset in pur1 is revised. ?note 1 is added. 32 table 5.2 recommended operating conditions (1) is partly revised. 33 table 5.3 recommended operating conditions (2) ?power supply ripple is deleted. (three items) figure 5.1 voltage fluctuation timing is deleted. 34 table 5.4 electrical characteristics (1) __________ ________ ?hold and rdy are added to hysteresis. ?hysteresis xin is deleted. 37 table 5.8 flash memory version electrical characteristics is revised. 38 table 5.12 memory expansion mode and microprocessor mode is added. 41 to 43 switching characteristics are added. 45 to 51 figures 5.4 to 5.10 timing diagram (2) to (8) are added. 52 to 66 characteristics of 3.3 v are added. 2.10 aug.25, 2006
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